1. Field of the Invention
The present invention relates to the packaging of integrated circuits and electronic components, and more particularly, to an improved package for use in flip-chip manufacturing of an underfilled integrated circuit package.
2. Description of the Related Art
Interconnection and packaging related issues are among the main factors that determine not only the number of circuits that can be integrated on a chip, but also the performance of the chip. These issues have increased in importance as advances in chip design have led to reductions in the sizes of features on transistors and enlargements in chip dimensions. Industry has come to realize that merely having a fast chip will not result in a fast system; it must also be supported by equally fast and reliable packaging.
Essentially, packaging supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Another important function of the package is simply to redistribute the tightly packed I/Os off the chip to the I/Os of a printed wiring board.
An example of a package-chip system is the “flip-chip” integrated circuit mounted on an area array organic package. Flip-chip mounting entails placing solder bumps on a die or chip, flipping the chip over, aligning the chip with the contact pads on a package substrate, and reflowing the solder balls in a furnace to establish bonding between the chip and the substrate. This method is advantageous in certain applications because the contact pads are distributed over the entire chip surface rather than being confined to the periphery as in wire bonding and most tape-automated bonding (TAB) techniques. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the chips. With flip-chip packaging, proper alignment of the chip and the package is essential to ensure proper operation of the final assembly.
It is known in the art of integrated circuit packaging to use underfill material to add structural integrity to an integrated circuit manufactured by the above-described flip-chip technology. Referring to FIGS. 1A-1C, a prior art process provides a package board 12 having a package surface 102, which has disposed thereon a plurality of connect pads, or cage pads (not shown), which are to be connected to a chip or die 14. A chip 14 having a plurality of solder bumps 16 disposed thereon is provided and placed on top of the package surface 102 so that the solder bumps 16 lie on package pads (not shown). The package board 12 and die 14 form an integrated circuit package assembly 10, which is placed in an oven (not shown) where it is heated so that the solder balls 16 melt (reflow) to form solder connections 18. The integrated circuit package assembly 10 is then withdrawn from the oven (not shown) and allowed to cool. There remain air gaps 104 between the die 14, the package surface 102, and the solder connections 16. Underfill material 106 is dispensed onto the package surface 102, where it flows by capillary action under the die 14 and around the solder connectors 16. The underfill material 106 displaces air in the gaps 104, 106 surrounds the solder connections 18, and forms an insulating structure around the solder connector as well as an adhesive bonding structure between the package board 12 and the dic 14, as seen in FIG. 1C. The underfill 106 acts as an adhesive between die 14 and package board surface 102, and thus increases the structural integrity of the integrated circuit package assembly 10, while protecting the solder connections 16 from chemical and mechanical wear.
Prior art methods of manufacturing an underfilled integrated circuit package assembly have disadvantages, however. One disadvantage to prior art processes is that a flat package board permits the die to move around thereon. Thus the die will often move and become misaligned after the die is positioned on the package board, but prior to reflowing of the solder balls. This results in defective products, with concomitant economic loss. Another disadvantage of prior art methods of manufacturing an integrated circuit is that prior art methods require that underfill material be applied in multiple iterations of small increments. This leads to increased process time, which increases economic costs. Additionally, prior art processes apply underfill material in layers, which results in a weaker adhesive effect than would be obtainable using a single layer of underfill material, since multiple layers have a tendency to separate or delaminate along the interstices of the layers. Also, prior art processes result in uneven application of underfill material, which often results in pockets of air remaining within the underfill material. These pockets of air can cause premature corrosion of solder connectors, uneven heat dissipation from the die, and other undesirable phenomena.